Comparators are frequently used in analog-to-digital converters (ADCs) to make decisions related to input signal voltage or current levels, where the decision is usually made with respect to a reference signal. On a circuit level, the comparator may be implemented using clocked latch circuitry. The clocked latch circuitry causes the output of the comparator to latch on high or low supply levels input to the comparator.
Successive Approximation Register ADCs (SAR-ADCs) are digital-to-analog converters that, in each conversion cycle, perform a sequence of comparisons and approximations (i.e. SA cycles) between the sampled input voltage and an internal digitally controlled reference, until the remaining difference is smaller than a predefined error threshold (VLSB). In practical implementations, the comparison function is implemented by a clocked comparator and the internal digitally controlled reference is implemented by a DAC (Digital to Analog Converter). In some SAR-ADC designs, a capacitive digital-to-analog converter (CDAC) holds the input sampled signal at the comparator inputs. In high-speed ADCs, smaller capacitors values of the CDAC are used to realize high conversion rates.
For each Successive Approximation (SA) loop in a conversion cycle, the comparator delay is a significant factor limiting the converter speed. The comparator delay has a component associated to the activation of the comparator after a rise in the clock signal. This delay is generally fixed and has a small dependency on the input voltage amplitude. Another delay component is associated with the comparator reset time. This delay is also considered generally constant and can be an important portion of the total fixed delay. The third component in the comparator delay is a variable delay associated with the comparator's regenerative response. This delay is a metastable delay and varies with the input signal amplitude, and therefore a bigger delay for smaller input amplitude.
In a SAR conversion cycle, each SA loop duration will have a variable minimum duration due to the comparator variable delay. If a synchronous clock scheme is used to trigger the comparator, the worst-case estimation for the comparator delay must be allocated in each SA loop.
Accordingly, there is a need for an ADC that addresses issues with delay in the SAR conversion cycle.